
	org	hcoreStartPc

	nop
	nop
	nop
	nop	;preload
	nop

	gssr	r127,0		;get core number
	cmpeq	last,0
	br.tc	notCoreZero
	nop			;delay slot
	nop			;delay slot
	nop			;delay slot
	nop			;delay slot
	nop
	
	;ldc test again
	
	move	hold,testData
	moveh	hold,last,>>testData
	or	r32,last,0

	move	hold,testDataWR
	moveh	hold,last,>>testDataWR
	or	r33,last,0

	
xLoop	
		
	ldc	r0,r32,0
	ldc	r1,r32,2
	ldc	r2,r32,4
	ldc	r3,r32,6
	ldc	r4,r32,8
	ldc	r5,r32,10
	ldc	r6,r32,12
	ldc	r7,r32,14
	ldc	r8,r32,16
	ldc	r9,r32,18
	ldc	r10,r32,20
	ldc	r11,r32,22
	ldc	r12,r32,24
	ldc	r13,r32,26
	ldc	r14,r32,28
	ldc	r15,r32,30
	
	st	r0,r33,0
	st	r1,r33,2
	st	r2,r33,4
	st	r3,r33,6
	st	r4,r33,8
	st	r5,r33,10
	st	r6,r33,12
	st	r7,r33,14
	st	r8,r33,16
	st	r9,r33,18
	st	r10,r33,20
	st	r11,r33,22
	br	xLoop
	st	r12,r33,24
	st	r13,r33,26
	st	r14,r33,28
	st	r15,r33,30
	
	
	
	; move	hold,testData
	; moveh	hold,last,>>testData
	; or	r1,last,0
	; nop
	; nop
	
	

	;ld hazard
	
	; ld	r8,r1,0
	; nop			;WAL nop
	; add	r8,r8,r8
	
	; ;ldc test
	
	; move	r5,3
	
; ldcTest
	
	; ldc	r2,r1,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r1,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r1,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r1,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r1,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r1,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r1,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r1,0
	; nop
	; or	r2,r2,r2
	
	; cmpeq	r5,0	
	; br.tc	ldcTest
	; sub	r5,r5,1
	; nop
	; nop
	; nop
	
	; ;ldc fail test
	
	; move	hold,hcoreStartPc
	; moveh	hold,last,>>hcoreStartPc
	; or	r3,last,0
	; nop
	; nop
	; move	r5,3
	
; ldcFailTest
	
	; ldc	r2,r1,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r3,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r1,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r3,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r1,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r3,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r1,0
	; nop
	; or	r2,r2,r2
	
	; ldc	r2,r3,0
	; nop
	; or	r2,r2,r2
	
	; cmpeq	r5,0	
	; br.tc	ldcFailTest
	; sub	r5,r5,1
	; nop
	; nop
	; nop
	
	;
	
notCoreZero	br	notCoreZero
	nop
	nop
	nop
	nop
	nop
	
testData	
	word	$00000001	
	word	$00000020
	word	$00000300
	word	$00004000
	word	$00050000	
	word	$00600000
	word	$07000000
	word	$80000000
	word	$09000000	
	word	$00a00000
	word	$000b0000
	word	$0000c000
	word	$00000d00	
	word	$000000e0
	word	$0000000f
	word	$0eeeeee0
	
testDataWR
	
	word	$00000000	
	word	$00000000
	word	$00000000
	word	$00000000
	word	$00000000	
	word	$00000000
	word	$00000000
	word	$00000000
	word	$00000000	
	word	$00000000
	word	$00000000
	word	$00000000
	word	$00000000	
	word	$00000000
	word	$00000000
	word	$00000000
	
	